DDR3 Stream FIFO CSR v1

SDB

RegIO

Reg 0x0 - Control, R/W

Reg 0x1 - Status, RO

Reg 0x2 - Log2 of DDR3 size in bytes, RO

Reg 0x4 - FIFO occupancy, 64 bits, RO

Reg 0x8 - ECC multiple errors counter, 32-bits, RO

Reg 0xA - ECC single error counter, 32-bits, RO

DDR3 Stream FIFO CSR v1 (last edited 2022-02-10 12:25:56 by sav)