/*
 *
 * ADCM-16 hardware settings and registers definition
 *
 */

#ifndef ADCM16_H
#define ADCM16_H 1

#include <sys/types.h>

#define ADCM_BOARD_NCH 16

#define ADCM_MIN_N_SAMP 4
#define ADCM_MAX_N_SAMP 254 /* hardware limit is 8192 */
#define ADCM_MIN_FRAGM_LEN ADCM_MIN_N_SAMP

#define ADCM_N_CH 32 /* maximum number of channels in system */
#define ADC_NCH ADCM_N_CH
//#define ADCM_BITS 10
//#define ADCM_BASELINE (1<<(ADCM_BITS-1))

#define ADC_REALSTEP 10e-9

#define ADC_TS_FREQ 1e8         /* timestamp counter clock, Hz */

//#define ADC_PREWIN_MIN 0
//#define ADC_PREWIN_MAX 31 -- this does not allow baseline reconstruction
//#define ADC_PREWIN_MAX 20

//#define ADC_MATCHWIN_MIN 1
//#define ADC_MATCHWIN_MAX 63

//#define ADC_LATENCY_MIN 0
//#define ADC_LATENCY_MAX 30
//#define ADC_LATENCY_OFFSET 0

#define ADC_MAX_GAIN 4095
#define ADC_DEFAULT_GAIN 700
#define ADC_GAIN_0dB 70
//#define ADC_MAX_DATA ((1<<ADCM_BITS)-1)
//#define ADC_MIN_DATA 0
//#define ADC_MAX_THR ADC_MAX_DATA
//#define ADC_MIN_THR ADC_MIN_DATA

#define ADCM_TRIG_RUN  0x8000
#define ADCM_TRIG_TEST 0x4000

#define ADCM_TRIGBIT_EXT1 0x1
#define ADCM_TRIGBIT_EXT2 0x2
//#define ADCM_TRIGBIT_EXT3 0x4
#define ADCM_TRIGBIT_INT  0x8

#define ADCM_CCTRL_BIT_CMPEN 0x0001
#define ADCM_CCTRL_BIT_S     0x0002
#define ADCM_CCTRL_BIT_M     0x0004
#define ADCM_CCTRL_BIT_TEST  0x0008
#define ADCM_CCTRL_BIT_ZERO  0x0010
#define ADCM_CCTRL_BIT_INV   0x0020

#endif /* ADCM16_H */
