=== ADC clock divider reset module ===

 * [[SDB Device ID]] 0x3ddcc6a5

==== Register Map ====

 * 0x00, Identification ''3ddcc6a5'', 32 bits, RO

 * 0x02, Control, R/W
  * [0] - enable divider reset(next pps)
  * [15:1] - reserved


 * 0x02, Status, R/W
  * [0] - adc phase ok
  * [14:1] - reserved
  * [15] - time valid

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[[CategorySDB|SDB]]