TRIG VME module registers

Hardware: TTCM, FVME2TM
See also FVME2TMWR_Ethernet_Registers

Module revisions by CR/CSR

0-3	reserved
4-7	TTCM version
8-11	MTDC-64 built-in, no counters
16	MTDC-64 built-in, interspill timer starts at end of spill, not start of spill, spill length is now 31 bits

Reg I/O

ttcm_core registers

CSR (ttcm_regio_slave_vmedaq)

AM 0x29 (A16 D32) Registers
Reg	Address	Name
0	0x0000	Control
1	0x0004	TRIGSet
2	0x0008	SPILLTimer1
3	0x000C	SPILLWidth
4	0x0010	TRIGDelay
5	0x0014	Timers
6	0x0018	Logic
7	0x001C	Test
8	0x0020	-
9	0x0024	Status
10	0x0028	NIMLogic
11	0x002C	LVDSEnable
12	0x0030	PulserPeriod
13	0x0034	Output Select
14	0x0038	TIMER_FREQ
15	0x003C	AUX Ctrl
16	0x0040	Serial ID [31:0]
17	0x0044	Serial ID [63:32]
18	0x0048	Temperature [15:0]
19	0x004C	-
20	0x0050	Firmware version [31:0]
21	0x0054	Firmware revision [31:0]
...
31	0x007C	-

ttcm_trig_counters

AM 0x29 (A16 D32) Registers
Reg	Address	Name
32	0x0080	number of read-out triggers
33	0x0084	number of all triggers
34	0x0088	lookup logic state 1 count, read-out
35	0x008C	lookup logic state 1 count, all
...
62	0x00F8	lookup logic state 15 count, read-out
63	0x00FC	lookup logic state 15 count, all

tmwr_vme_regs

TMWR VME Registers

vme_xoff_counters_regs

Reg	Address	Name
128	0x0200	xoff on timer[31:0]
129	0x0204	xoff on timer[63:32]
130	0x0208	xoff off timer[31:0]
131	0x020C	xoff off timer[63:32]
132	0x0210	-
...
135	0x021C	-

tm_counters

Reg	Address	Name
256	0x0400	blocked/unblocked input lvds hit counters
...
383	0x05FC	end of hit counters(40+40, last 16 unused)

Supports base registers: Control, Status.

Status register supports bits: 0 (TTC clock status).

Detailed Description

AM 0x29, A16 D32

Write 0 to all reserved values.

Reg 1, @0x0004, TRIGSet, R/W

[0] external spill enable (SPILL input)
[1] NIM1..NIM7 trigger input enable
[2] Ext and soft spill mode: 1 - gate (no timer), 0 - pulse (use spill timer)
[3] Software spill
[4] internal spill timer enable
[5] internal trigger test pulser enable
[6] enable XOFF wait
[7] pulser enable
[15:8] LVDS32...LVDS1 input enable, grouped by 4
[22:16] NIM7..NIM1 input enable
[23] reserved
[30:24] NIM7..NIM1 input inversion
[31] reserved

Reg 2. @0x0008, SPILLTimer1, R/W

[15:0] spill delay, 1 ms step
[31:16] spill repeat interval, 1 ms step

Reg 3, @0x000C, SPILLWidth, R/W

[30:0] spill duration, 1 ms step (revisions before 16 use bits 15:0 only)
[31] enable spill extension for CBLT

Reg 4, @0x0010, TRIGDelay, R/W

[3:0] ST trigger delay, 12.5 ns step
[7:4] TQDC1 trigger delay, 12.5 ns
[11:8] TQDC2 trigger delay, 12.5 ns
[15:12] NIM trigger delay, 12.5 ns
[19:6] trigger word readout adjustment, 12.5 ns
[21:20] OUT clock adjustment, 25ns (used with BRIC)
[23:22] reserved
[31:24] input shaper, 12.5 ns step (12.5 - 3200 ns)

Reg 5, @0x0014, Timers, R/W

[3:0] TTC trigger output delay, 50 ns step
[7:4] (XOFF wait time, 50 ns step)
[31:16] data read request (IRQ5) delay adjustment, 50 ns step

Reg 6, @0x0018, Logic, R/W

[15:0] trigger logic lookup bits
[31:16] reserved

Reg 10, @0x0028, NIMLogic, R/W

[2:0] Low Majority Threshold for NIM inputs (default 1)
[5:3] High Majority Threshold (default 7)
[31:6] reserved

Reg 11, @0x002C, LVDSEnable, R/W

[31:0] - LVDS inputs enable

Reg 12, @0x0030, PulserPeriod, R/W

[31:0] - pulser period time setup

Reg 13, @0x0034, Output Select, R/W

[3:0] - Output 1 select
[7:4] - Output 2 select
[11:8] - Output 3 select
[15:12] - Output 4 select
[31:16] - reserved

Reg 15, @0x003C, AUX Ctrl, R/W

[0] Enable reading input hit counters on trigger
[31:1] - reserved

Output select code

#	Dir	Function
0	Out	Logic 0
1	Out	Logic 1
2	Out	Spill (gate)
3	Out	XOFF (dead time)
4	Out	Trigger (all)
5	Out	Trigger (accepted)
6	Out	Trigger (rejected)
7	Out	Pulser (Hz)
8	Out	Pulser (Noise)
9	Out	BRIC strobe (10 MHz)
10	Out	1/3 PPS
11	Out	1 PPS
12	In	XOFF input, 50Ω
13	In	Trigger input, 50Ω
14	In	Spill input, 50Ω
15	In	Run Reset input, 50Ω

Reg 14, @0x0038, TIMER_FREQ, R/O

[31:0] - Timestamp frequency, Hz

Scaler Registers

TRIG has 32-bit scalers for counting trigger lookup logic states. Counters are enabled by TTC SPILL signal. For each trigger state there are two counters. One counts all states - including lost triggers, another counts only read-out states. The difference is the number of lost triggers due to dead-time.

Scaler registers are R/W. Counter is reset by rising edge of TTC SPILL signal, i.e. at the beginning of spill.

See ttcm_trig_counters.

VMEDAQ Registers | TMWR