= TQDC16VS VME module registers, firmware v2.0 = Similar boards registers: [[VmeRegistersTqdc16v1|TQDC-16 Firmware v1.0]], [[VmeRegistersTqdc16|TQDC-16 Firmware v2.0]] Hardware: [[TQDC16VS]] ||AM 0x29 (A16 D32) Registers|| ||Reg||Address||Name||Access|| ||0||0x0000||Control||R/W|| ||1||0x0004||ADCSet0||R/W|| ||2||0x0008||ADCSet1||R/W|| ||3||0x000C||JTAG||R/W|| ||4||0x0010||[[#TRIGSet|TRIGSet]]||R/W|| ||5||0x0014||DACSet||R/W|| ||6||0x0018||ADCLat||R/W|| ||7||0x001C||factory test||R/W|| ||8||0x0020||JTAG32||R/W|| ||9||0x0024||Status||Read Only|| ||10||0x0028||Compstate||Read Only|| ||11||0x002C||ADC Window||R/W|| ||12||0x0030||TQDC16VS gain control||R/W|| ||<:-4>unused|| ||16||0x0040||Serial_ID_lo||Read Only|| ||17||0x0044||Serial_ID_hi||Read Only|| ||18||0x0048||Temperature_1||Read Only|| ||<:-4>unused|| ||32||0x0080||ADC 0 data||Read Only|| ||<:-4>...|| ||47||0x00BC||ADC 15 data||Read Only|| Supports [[VmeInterfaceGeneral|base registers]]: Control, JTAG, JTAG32, Status, Serial_ID_1, Temperature_1. Status register supports bits: 0, 2, 3. == SPI communication to ADCs (Base 0x0100, Mask 0x003C) == [[#SPI_ADC|Details]] ||Reg||Address||Name|| ||0||0x0000||ADC0 SPI address|| ||1||0x0004||ADC0 SPI write data|| ||2||0x0008||ADC0 SPI read data|| ||<:-3>unused|| ||8||0x0020||ADC1 SPI address|| ||9||0x0024||ADC1 SPI write data|| ||10||0x0028||ADC1 SPI read data|| == Deserializers Control & Status (Base 0x0140, Mask 0x003C) == ||Reg||Address||Name|| ||0||0x0000||Deserializers Control|| ||1||0x0004||Deserializers Status|| ||2||0x0008||Reserved|| ||3||0x000C||IDELAY Tap Value|| ||4||0x0010||IDELAY Load Mask|| == MCU SPI Slave (Base 0x0180, Mask 0x003C), Read only == ||Reg||Address||Name|| ||0||0x0000||Reserved|| ||1||0x0004|||| ||2||0x0008|||| ||<:-3>All others - reserved|| ||AM 0x39 (A24 D32) Registers|| ||Reg||Address||Name|| ||0||0x000000||Trigger Logic RAM 0, word 0|| ||<:-3>...|| ||7||0x00001C||Trigger Logic RAM 0, word 7|| ||8||0x000020||Trigger Logic RAM 1, word 0|| ||<:-3>...|| ||15||0x00003C||Trigger Logic RAM 1, word 7|| ||200||0x000800||Counter0|| ||<:-3>...|| ||215||0x00083C||Counter15|| == Additional Registers == AM 0x29, A16 D32 Reg 1, @0x0004, ADCSet0, R/W ADC device 0, channels 0..7 . [9:0] search window . [14:10] --(match window)-- . [15] input polarity (1=negative) . [23:16] channels 7:0 enable mask . [29:28] --(device number ('device' field in raw data), set to 1)-- set to 0 . [31:30] mode Reg 2, @0x0008, ADCSet1, R/W ADC device 1, channels 8..15 . [9:0] --(search window)-- . [14:10] --(match window)-- . [15] input polarity (1=negative) . [23:16] channels 15:8 enable mask . [29:28] --(device number ('device' field in raw data), set to 2)-- set to 0 . [31:30] mode <> Reg 4, @0x0010, TRIGSet, R/W . [3:0] hit matching width . [7:4] select channel A for ST trigger . [11:8] select channel B for ST trigger . [12] ST channel A enable . [13] ST channel B enable . [14] reserved . [15] 1 - AND matching, 0 - XOR matching (?) . [31:16] channels 15:0 enable mask for trigger logic Reg 5, @0x0014, DACSet, R/W . [15:0] DAC data . [16] select: 0 - channels 7:0, 1 - channels 15:8 . [17] LDAC (load command) Reg 6, @0x0018, ADCLat, R/W . [31:0] ADC trigger latency, complementary code Reg 10, @0x0028, Compstate, Read only . [15:0] input discriminator state Reg 11, @0x002C, ADC Window, R/W . [31:0] ADC Window (approx 1.5us max) Reg 12, @0x0030, Gain Control, R/W . [0] channels 1-2 gain: 0 - x1 gain, 1- x4 gain . [1] channels 3-4 gain: 0 - x1 gain, 1- x4 gain . [2] channels 5-6 gain: 0 - x1 gain, 1- x4 gain . [3] channels 7-8 gain: 0 - x1 gain, 1- x4 gain . [4] channels 9-10 gain: 0 - x1 gain, 1- x4 gain . [5] channels 11-12 gain: 0 - x1 gain, 1- x4 gain . [6] channels 13-14 gain: 0 - x1 gain, 1- x4 gain . [7] channels 15-16 gain: 0 - x1 gain, 1- x4 gain . [31:8] reserved Reg 32..Reg 47, @0x0080..@0x00BC, ADC instant data . [5:0] reserved 0 . [15:6] ADC raw sample data . [31:16] reserved <> === SPI communication to ADCs (Base 0x0100, Mask 0x003C) === Reg 0, @0x0000, ADC0 SPI address . [6:0] SPI address . [7] SPI read/write command (1 - read) . [31:8] reserved Reg 1, @0x0004, ADC0 SPI write data . [7:0] SPI write data . [31:8] reserved Reg 2, @0x0008, ADC0 SPI read data . [7:0] data from registers related to ADC channels 1 4 5 8 . [15:8] data from registers related to ADC channels 2 3 6 7 . [31:16] reserved Reg 8, @0x0020, ADC1 address . [6:0] SPI address . [7] SPI read/write command (1 - read) . [31:8] reserved Reg 9, @0x0024, ADC1 write data . [7:0] SPI write data . [31:8] reserved Reg 10, @0x0028, ADC1 SPI read data . [7:0] data from registers related to ADC channels 1 4 5 8 . [15:8] data from registers related to ADC channels 2 3 6 7 . [31:16] reserved === Deserializers Control & Status (Base 0x0140, Mask 0x003C) === Reg 0, 0x0000, Deserializers Control . [13:0] Reserved . [14] Deserializers reset . [15] Reserved Reg 1, 0x0004, Deserializers Status . [0] Deserializer №0 lock . [1] Deserializer №0 unlock detected . [2] Deserializer №1 lock . [3] Deserializer №1 unlock detected . [4] Deserializer №2 lock . [5] Deserializer №2 unlock detected . [6] Deserializer №3 lock . [7] Deserializer №3 unlock detected . [15:8] Reserved Reg 2, 0x0008, Reserved Reg 3, 0x000C, IDELAY Tap Value . [4:0] IDELAY Taps . [15:5] Reserved Reg 4, 0x0010, IDELAY Load Mask . [0] Deserializer №0 bit clock delay load . [1] Deserializer №0 data delay load . [2] Deserializer №1 bit clock delay load . [3] Deserializer №1 data delay load . [4] Deserializer №2 bit clock delay load . [5] Deserializer №2 data delay load . [6] Deserializer №3 bit clock delay load . [7] Deserializer №3 data delay load . [15:8] Reserved ---- [[CategoryVmedaqRegisters|VMEDAQ Registers]]