= MSC16V VME module registers =

Hardware: [[MSC16V]] [[MSC16VE]]

||<tablewidth="60%" : -4>AM 0x29 (A16 D32) Registers||
||Reg||Address||Name            ||Access   ||
||0  ||0x0000 ||Control         ||R/W      ||
||<:-4>unused ||
||5  ||0x0014 ||DACSet          ||R/W      ||
||6  ||0x0018 ||Step Timer set  ||R/W      ||
||7  ||0x001C ||Test            ||R/W      ||
||8  ||0x0020 ||Channel grouping||R/W      ||
||9  ||0x0024 ||Status          ||Read Only||
||10 ||0x0028 ||Compstate       ||Read Only||
||11 ||0x002C ||Ram Size        ||Read Only||
||12 ||0x0030 ||PCB Type Code   ||Read Only||
||<:-4>unused ||
||16 ||0x0040 ||Serial_ID_lo    ||Read Only||
||17 ||0x0044 ||Serial_ID_hi    ||Read Only||
||18 ||0x0048 ||Temperature_1   ||Read Only||
||<:-4>unused ||
||32 ||0x0080 ||Counter 0 data  ||Read Only||
||<:-4>...||
||47 ||0x00BC ||Counter 15 data ||Read Only||

||<tablewidth="50%" : -3>AM 0x39 (A24 D32) RAM Access||
||<:-4>0x000000 - 0x7FFFFF 2Mx32 RAM||

Supports [[VmeInterfaceGeneral|base registers]]: Control, Status, Serial_ID_1, Temperature_1.

Status register supports bits: 0

== Additional Registers ==
AM 0x29, A16 D32

Reg 5, @0x0014, DACSet, R/W
 . [15:0] - DAC data
 . [16] - select: 0 - channels 7:0, 1 - channels 15:8
 . [17] - LDAC (load command)

Reg 6, @0x0018, STEPTIMER, R/W
 . [15:0] - Step Timer data, default value 400 (0x0190)
 . [30:16] - reserved
 . [31] - Step Timer control: 1 - enable, 0 - disable

Reg 8, @0x0020, Channel grouping, R/W
 . [0] - when set: 16 channels, 7-bit counter per channel
 . [1] - when set: 8 channels, 14-bit counter per channel
 . [2] - when set: 4 channels, 28-bit counter per channel
 . [31:3] - reserved

Reg 10, @0x0028, Compstate, Read only
 . [15:0] - input discriminator state

Reg 11, @0x002C, Ram Size, Read only
 . [7:0] - channel sample count log2 value
 . [15:8] - channel count log2 value (4 for MSC16V)

Reg 12, @0x0030, PCB Type Code, Read Only
 . [15:0] - PCB Type Code: 0x0210 - MSC16VE v1.0, 0x0110 - MSC16V v1.0
 . [31:16] - reserved

Reg 32..Reg 47, @0x0080..@0x00BC, instant counters data
 . [31:0] - counter data

== Spill Hit Counters, RO (Base 0x0100, Mask 0x003C) ==
||<tablewidth="60%" : -4>AM 0x29 (A16 D32) Registers||
||Reg ||Address||Name        ||Access   ||
|| 0  ||0x0000 ||Counter Ch0 ||Read Only||
|| 1  ||0x0004 ||Counter Ch1 ||Read Only||
||<:-4> ... ||
|| 14 ||0x0038 ||Counter Ch14||Read Only||
|| 15 ||0x003C ||Counter Ch15||Read Only||

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[[CategoryVmedaqRegisters|VMEDAQ Registers]]