= TTB module registers =

Hardware: [[TTB9V]]

Registers are 16 bit width. 32-bit and 64-bit data is packed as following:
||Reg #||64-bit word||
||0x70||bits 15:0||
||0x71||bits 31:16||
||0x72||bits 47:32||
||0x73||bits 63:48||

== Register I/O ==

||address||Module||
||0x0040 - 0x005F||[[MlinkCsr|M-Link CSR]]||
||0x0100 - 0x01FF||[[TTB_CSR|TTB Control and Status]]||
||0x0200 - 0x02FF||[[TTB_Statistic|Statistic Counters]]||
||0x0300 - 0x030F||UTC Time||
||0x0400 - 0x040F||[[TTB_Hosts_Serial_IDs|TTB Hosts Serial IDs]]||
||0x1000 - 0x13FF||[[TTB_SPILL_BUSY_COUNTERS|Spill & Busy counters]]||

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[[CategoryHrb|HRB]] [[CategoryMlinkRegisters|MLinkRegisters]]