#<> = TTVXS Module Registers, version 1.0 = * Hardware: [[TTVXS]] * SDB * [[https://afi-git.jinr.ru/fpga/ttvxs/-/blob/sdb-test/top/ttvxs.sdb.csv|ttvxs.sdb.csv]] (Git) * [[attachment:ttvxs.sdb.csv]] (copy) ---- == Register I/O == Registers are 16 bit width. 32-bit and 64-bit data is packed as following: ||Reg # ||64-bit word || ||0x70 ||bits 15:0 || ||0x71 ||bits 31:16 || ||0x72 ||bits 47:32 || ||0x73 ||bits 63:48 || ||<:>'''Address range'''||<:>'''Module''' || ||0x0040 ~ 0x001F ||[[#SYS_REG_CSR|CSR]] || ||0x0200 ~ 0x02FF ||[[#SYS_REG_RC|TTVXS Run Control Core Registers]] || ||0x0800 ~ 0x08FF ||[[WR_Status_Registers|White Rabbit Status Registers]] || ||0x0900 ~ 0x09FF ||[[#SYS_REG_STAT|Statistics Readout CSR]] || ||0x1000 ~ 0x10FF ||[[HWIP_Error_Counters|HWIP Error Counters]] || ||0x1200 ~ 0x13FF ||[[TTVXS_Run_Control_Counters|TTVXS Run Control Counters]] || ||0x4000 ~ 0x40FF ||[[MCU Registers v2.0]]|| ||0x5000 ~ 0x51FF ||SFP0 [[Network Port Registers]]|| ||0x5800 ~ 0x58FF ||[[#SysErr|System errors counters]]|| ||0x6000 ~ 0x6FFF ||18x [[felink_v1_csr|FE-Link CSR v1.0]]|| ||0x7000 ~ 0x70FF ||[[SPI_NOR_Flash_Programmer|Flash Programmer]]|| ||0x7C00 ~ 0x7FFF ||[[CategorySDB|SDB]]|| ---- == Registers description == <> === CSR === '''Base address - 0x0040, address mask - 0x001F.''' Reg 0x0000 - Control, R/W . [15] - run enable, default 1 (''used since r28390, before was in addr 0x0200'') . [14:2] - reserved . [1] - Counters Lock . [0] - Softclear Reg 0x0001 - reserved Reg 0x0002 - [[DeviceId|Device ID]], RO Reg 0x0003~0x0005 - reserved Reg 0x0006 - Serial ID MSB, RO Reg 0x0007 - reserved Reg 0x0008 - Live Magic, R/W Reg 0x0009 - reserved Reg 0x000a - reserved Reg 0x000b - Board Temperature, RO Reg 0x000c - F/W Version, RO Reg 0x000d - F/W Revision, RO Reg 0x000e - Serial ID LSB, RO Reg 0x000f - M-Stream config, RO . [15:4] - reserved . [3] - m-stream multi-ack . [2:0] - log2 from number of retransmitting buffers Reg 0x0010 - OneWire ID (64-bit), RO Reg 0x0014 - reserved Reg 0x0015 - PCB Version, RO . [15:8] - major bits . [7:0] - minor bits Reg 0x0016 - Status (all bits active-low), RO . [15:5] - reserved . [4] - MCU present . [3] - System Power Good . [2] - VXS ACFAIL . [1] - VXS SYSFAIL . [0] - VXS SYSRESET Reg 0x0017 - reserved Reg 0x0018 - MGT Synchronization status (for test, added in r28832), 32-bits, RO . [31:22] - reserved . [21:20] - SFP[3:2] . [19] - FMC DP0 . [18] - VXS SP1 . [17:0] - VXS PP[17:0] ---- <> === Run Control Core Registers === '''Base address - 0x0200, address mask - 0x00FF.''' ''For all timers clock period is 8 ns.'' Reg 0x0000 - rc_ctrl, R/W . [15] - --(run enable (default 1))-- (''obsolete since r28390, moved to [[#SYS_REG_CSR|CSR]] addr 0x0040'') . [14] - send timestamp reset to payloads . [13] - reset AUX counters for trigger data . [12] - enable AUX counters readout in trigger data (counters continue to count if disabled for readout) . [11:2] - reserved . [1] - softreset (''since 1.4.6, previously - reserved'') . [0] - clear Reg 0x0001 - Reserved, RO Reg 0x0002 - Trigger Source Select, R/W . [15] - fixed frequency pulser . [14] - random pulser . [13:2] - reserved . [1] - --(digital input (SFP))-- - not yet implemented . [0] - LEMO input Reg 0x0003 - Trigger State, RO Reg 0x0004 - Busy Input Mask (32-bit), R/W Reg 0x0006 - Busy Input State (32-bit), RO Reg 0x0008 - Busy Timeout State (32-bit), RO Reg 0x000A - Fixed Frequency Pulser Period (32-bit), R/W Reg 0x000C - Random Pulser Probability (32-bit), R/W Reg 0x000E - Random Pulser Dead Time (32-bit), R/W Reg 0x0010 - Queue of Triggers to Readout, R/O Reg 0x0011 - Module Busy Status . [15:2] - reserved . [1] - trig_data busy . [0] - readout busy Reg 0x0012 - Busy Source Select, R/W . [15:2] - reserved . [1] - FE-Link busy . [0] - VXS busy Reg 0x0013 - Reserved, RO Reg 0x0014 - Event Number Load (64-bit), R/W . ''Event number will be updated when writing into reg 0x0017 performed'' Reg 0x0018 - Current Event Number (64-bit), RO Reg 0x0016-0x001F - Reserved Reg 0x0020 - Build Parameters (128-bit), RO ---- <> === White Rabbit Status Registers === * '''Base address - 0x0800, address mask - 0x00FF.''' * [[WR_Status_Registers|WR Status Registers]] * Module specific register 0x000E: Number of Divider-by-3 Synchronization Error events ---- <> === Statistics Readout CSR === '''Base address - 0x0900, address mask - 0x00FF.''' Reg 0x0000 - Control, R/W . [15:14] - reserved . [0] - enable statistics readout (enable by default) Reg 0x0001 - Reserved Reg 0x0002 - Statistics Readout Interval, 1 ms step, R/W . ''minimum time interval between events with statistics data,'' . ''1000 ms by default, maximum 65535 ms'' Reg 0x0003 - reserved Reg 0x0004 - Number of registers to read into Statistic Data Block . ''actual value to send is (N-1)'' Reg 0x0005 - Statistic RAM write address . ''should be less or equal to number of registers'' . ''to read into statistic (Reg 0x0004)'' Reg 0x0006 - Statistic RAM write data . ''specifies RegIO address to read into statistic,'' . ''this value stores in Statistic RAM in address'' . ''set by Reg 0x0005'' ---- <> === System errors counters === '''Base address - 0x5800, address mask - 0x00FF.''' 32 bits counters. . 0x00 - statistics regio error . 0x02 - ethernet regio error . 0x04 - ce_24ns unlocked . 0x06 - ts upscaler unlocked . 0x08 - divider-by-3 error . 0x0A - WR time error . 0x0C - MCU regio timeout . 0x0E - MCU SPI crc error . 0x10 - MCU regio error . 0x12 - any regio masters arbiter error ---- [[CategoryMlinkRegisters|MLinkRegisters]]