= TTB Spill & Busy Counters =

Hardware: [[TTB9V]]

Registers are 16 bit width. 32-bit and 64-bit data is packed as following:
||Reg #||64-bit word||
||0x70||bits 15:0||
||0x71||bits 31:16||
||0x72||bits 47:32||
||0x73||bits 63:48||

== Register I/O ==

All registers are 64-bits counters, read only.
Base address - 0x1000.
Address mask - 0x03FF.

||Reg #||Address ||Description              ||
||   0 || 0x0000 || Spill Counter           ||
||   1 || 0x0004 || TTB Busy Counter        ||
||   2 || 0x0008 || Channel #0 Busy Counter ||
||   3 || 0x000C || Channel #1 Busy Counter ||
||   4 || 0x0010 || Channel #2 Busy Counter ||
||   5 || 0x0014 || Channel #3 Busy Counter ||
||   6 || 0x0018 || Channel #4 Busy Counter ||
||   7 || 0x001C || Channel #5 Busy Counter ||
||   8 || 0x0020 || Channel #6 Busy Counter ||
||   9 || 0x0024 || Channel #7 Busy Counter ||
||  10 || 0x0028 || Channel #8 Busy Counter ||