TTB Control and Status Registers

Hardware: TTB9V

Registers are 16 bit width. 32-bit and 64-bit data is packed as following:

Reg #

64-bit word

0x70

bits 15:0

0x71

bits 31:16

0x72

bits 47:32

0x73

bits 63:48

Register I/O

address

Description

0x100

TTB Control

R/W

0x101

TTB Status

RO

0x102

Link Enable

R/W

0x103

Link Status

RO

0x104

Errdisable Status

RO

0x105

Busy Status

RO

0x106

Pulser Period [15:0]

R/W

0x107

Pulser Period [31:16]

R/W

0x108

Event Number [15:0]

RO

0x109

Event Number [31:16]

RO

0x10A

Errdisable Recovery Time [15:0]

R/W

0x10B

Errdisable Recovery Time [31:16]

R/W

0x10C

Errdisable Mask

R/W

0x10D

0x10E

Spill Number [15:0]

RO

0x10F

Spill Number [31:16]

RO

0x110

RX 0 Status

RO

0x111

RX 1 Status

RO

0x112

RX 2 Status

RO

0x113

RX 3 Status

RO

0x114

RX 4 Status

RO

0x115

RX 5 Status

RO

0x116

RX 6 Status

RO

0x117

RX 7 Status

RO

0x118

RX 8 Status

RO

...

0x11C

Global Event Number [15:0]

R/W

0x11D

Global Event Number [31:16]

R/W

0x11E

Global Event Number [47:32]

R/W

0x11F

Global Event Number [63:48]

R/W

...

0x1FF


HRB CSR MLinkRegisters

TTB_CSR (last edited 2020-08-18 10:32:05 by islepnev)