= HRB module registers =

Hardware: [[HRB128E]], [[HRB6ASD]]

Registers are 16 bit width. 32-bit and 64-bit data is packed as following:
||Reg #||64-bit word||
||0x70||bits 15:0||
||0x71||bits 31:16||
||0x72||bits 47:32||
||0x73||bits 63:48||

== Register I/O ==

||address||Module||
||0x040 - 0x05F||[[MlinkCsr|M-Link CSR]]||
||0x100 - 0x1FF||[[#REG_HC_BASE|Hit Counters]]||
||0x200 - 0x207||[[#REGHRBCORE|HRB Core]]||
||0x300 - 0x30F||[[#REG_TTC|TTC link]]||
||0x310 - 0x310||[[#REG_DAC|Threshold DAC]] (HRB6ASD)||
||0x320 - 0x32F||[[#REG_PULSER|Test Pulser]] (HRB6ASD)||

||address||Description||
||0x40||[[#REGCONTROL|Control]]||
||0x41||[[#REGSTATUS|Status]]||
||0x42||[[#REGDEVICEID|Device ID]]||
||0x43||[[#REGTEST|LiveMagic]]||
||0x44||[[#REGDATAWIN|Data Window]]||
||0x45||[[#REGTRIGLATENCY|Trigger Latency]]||
||0x46||[[#REGTTCSTATE|TTC State]]||
||0x47||[[#REGTRIGSRC|Trigger Source]]||
||0x48||[[#REGTRIGTIMER|Trigger Timer]]||
||0x49||[[#REGSPILLCTRL|Spill Control]]||
||0x4A|| ||
||0x4B|| ||
||0x4C|| ||
||0x4D|| ||
||0x4E|| ||
||0x4F||[[#REGMSTRCONFIG|M-Stream Config]]||
||0x50-0x53||[[#REGSERIALID|64-bit Serial ID]]||
||0x54||[[#REGTEMPERATURE|Temperature]]||
||0x55|| ||
||0x56||[[#REGFWVER|Firmware Version]]||
||0x57||[[#REGFWREV|Firmware Revision]]||
||0x58-0x5F||[[#REGINSTATE|Input State]]||
||0x60-0xFF|| ||
||0x100-0x1FF||[[#REGHCBASE|Hit Counters]]||
||0x200-0x207||[[#REGHRBCORE|HRB Core Registers]]||
||0x208-0x2FF|| ||
||0x300-0x30F||[[#REGTTC|TTC Link Error Counters]]||
||0x310||[[#REGDAC|Threshold DAC]]||
||0x311-0x31F|| ||
||0x320-0x32F||[[#REGPULSER|Test Pulser]]||

<<Anchor(REGCONTROL)>>

== M-Link CSR ==

Reg 0x40, CTRL, R/W
 . [0] - softclear (clear statistics)
 . [1] - counters lock (0 - counters enable, 1 - lock)
 . [11:2] - reserved
 . [12] - disable 0xFEFE address decode
 . [13] - reserved
 . [14] - reserved
 . [15] - reserved

<<Anchor(REGSTATUS)>>
Reg 0x41, Status, R/O
 . [3:0] - clock status {fmc, ttc, lemo, mux}
 . [7:4] - selected clock {fmc, ttc, lemo, osc}
 . [15:8]  - reserved

<<Anchor(REGDEVICEID)>>
Reg 0x42, DEVICE_ID, RO
 . [15:8] - [[DeviceId|device id]]
 . [7:0] - reserved (0)

<<Anchor(REG_TEST)>>
Reg 0x43, Live Magic, R/W
 . [15:0] - data

<<Anchor(REGDATAWIN)>>
Reg 0x44, Data Window
 . [15:0]  - value, range 0 - 1023

<<Anchor(REGTRIGLATENCY)>>
Reg 0x45, Trigger Latency
 . [15:0]  - value, range 0 - 1023

<<Anchor(REGTTCSTATE)>>
Reg 0x46, TTL/LVDS state
 . [1:0]   - TTL input state
 . [3:2]   - reserved
 . [4]     - LVDS spill state
 . [5]     - LVDS trig state
 . [6]     - LVDS busy state
 . [7]     - reserved
 . [8]     - TTC clock ok
 . [9]     - TTC link0(trig) sync ok(current state)
 . [10]    - TTC link1(timestamp) sync ok(current state)
 . [15:11] - reserved

<<Anchor(REGTRIGSRC)>>
Reg 0x47, Trigger Source
 . [0]    - enable TTL spill (P13-top)
 . [1]    - enable TTL trigger (P13-bot)
 . [2]    - enable LVDS spill (P11)
 . [3]    - enable LVDS trigger (P11)
 . [4]    - enable internal spill
 . [5]    - enable internal trigger
 . [15:6] - reserved

<<Anchor(REGTRIGTIMER)>>
Reg 0x48, Trigger Timer
 . [15:0] - trigger interval (*8ns)

<<Anchor(REGSPILLCTRL)>>
Reg 0x49, Spill Control
 . [15] - soft spill
 . [14:0] - reserved

<<Anchor(REGMSTRCONFIG)>>
Reg 0x4F - M-Stream config
 . [15:4] - reserved
 . [3]    - m-stream multi-ack
 . [2:0]  - log2 from number of retransmitting buffers

<<Anchor(REGSERIALID)>>
Reg 0x50, SERIAL_ID, 64-bit Board Serial Number (DS18B20), RO

<<Anchor(REGTEMPERATURE)>>
Reg 0x54, TEMPERATURE, current temperature, RO

Reg 0x55, reserved, RO

<<Anchor(REGFWVER)>>
Reg 0x56, FW_VER, 16-bit, firmware version number, RO

<<Anchor(REGFWREV)>>
Reg 0x57, FW_REV, 16-bit, firmware revision number, RO

<<Anchor(REGINSTATE)>>
Reg 0x58 - 0x5F, Input State, RO


<<Anchor(REGHCBASE)>>

== Input Hit Counters ==

Reg 0x100 - 0x1FF, 256 x 16-bit input hit counters, RO

<<Anchor(REGHRBCORE)>>

== HRB Core ==

Reg 0x200, core control register, R/W
 . [0] - timestamp mode, reset ~every 1.4 sec(default) or continuous 
 . [1] - enable stream readout

Reg 0x201, minimum input hit duration, R/W
 . [15:4] - reserved
 . [3:0] - duration set (2 ns step, max 32 ns ~ 0xF)

Reg 0x202, 32bit trigger pass counter, RO

Reg 0x204, 32bit trigger block counter, RO

Reg 0x206, 32bit event number, RO

Reg 0x208, 32bit spill number, R/W

Reg 0x20A, 32bit busy timeout counter, RO

Reg 0x20C, 64bit system timestamp, RO

Reg 0x210, 64bit busy ON timer while spill, RO

Reg 0x214, 64bit busy OFF timer while spill, RO

Reg 0x218, 64bit global event number, R/W

Reg 0x21C, number of words in mstream FIFO, RO

Reg 0x220, 64bit mstream busy ON timer while spill, RO

Reg 0x224, 64bit mstream busy OFF timer while spill, RO

<<Anchor(REG_TTC)>>

== TTC Link Error Counters, 32 bit ==

Reset counters by softclear (CTRL bit 0)

||0x300||ts_zero_mismatch||
||0x302||TTC TRIG sync loss||
||0x304||TTC TRIG code error||
||0x306||TTC RESET sync loss||
||0x308||TTC RESET code error||
||0x30A-0x30E||unused||

<<Anchor(REG_DAC)>>

== Threshold DAC ==

Reg 0x310, Threshold DAC

<<Anchor(REG_PULSER)>>

== Test Pulser ==

Reg 0x320, Random pulser enable mask
 . [5:0] enable mask

Reg 0x321, Periodic pulser enable mask
 . [5:0] enable mask

Reg 0x322, External pulser enable mask
 . [5:0] enable mask

Reg 0x323, unused

Reg 0x324, 32bit pulser 0 period

Reg 0x326, 32bit pulser 1 period

Reg 0x328, 32bit pulser 2 period

Reg 0x32A, 32bit pulser 3 period

Reg 0x32C, 32bit pulser 4 period

Reg 0x32E, 32bit pulser 5 period

----
[[CategoryHrb|HRB]] [[CategoryMlinkRegisters|MLinkRegisters]]