FVME Registers

Version 1.0 Registers

*Note: all values in hex

Registers are 16 bit wide. 32-bit and 64-bit data is packed as following:

FVME control (0000 - 000F)

0000 - General Control (R/W)

• [2:0] - reserved Spill source select (IRQ7..IRQ1, TTC)

• [5:3] - reserved Trigger source select (IRQ7..IRQ1, TTC)

• [6] - softclear (break cycle)
• [7] - stat_clr (clear statistic counters)
• [8] - stat_lock (stop increment statistic counters)
• [9] - drive SYSRESET*
• [10] - cycle abort
• [15:11] - reserved

0001 - Run Mode Control (R/W)

• [14:0] - reserved
• [15] - RUN mode enable

0002 - Program mode VME AM, flags (R/W)

• [5:0] - Address Modifier code
• [12:6] - reserved
• [13] - WRITE enable (1:write, 0:read)
• [14] - IACK* state (0: active)
• [15] - CBLT enable

0003 - RUN mode VME AM, flags (R/W)

• [5:0] - Address Modifier code
• [12:6] - reserved
• [13] - WRITE enable (1:write, 0:read)
• [14] - IACK* state (0: active)
• [15] - CBLT enable

0004 - VME Address A[31:0] (R/W, 32 bit)

0006 - VME Write Data D[31:0] (R/W, 32 bit)

0008 - VME Read Data D[31:0] (R, 32 bit)

000A - VME Operation and System Status (R)

• [0] - Timeout
• [1] - DTACK
• [2] - BERR
• [3] - normal cycle granted
• [4] - auto cycle granted
• [5] - any transfer active
• [6] - SPILL active
• [7] - ACFAIL asserted
• [8] - SYSFAIL asserted
• [15:9] - IRQ7..IRQ1

000B - reserved (R)

• [15:0] - reserved

000C - Test register (R/W, 32 bit)

000E - Spill Wordcount SPWC[31:0] (R, 32 bit)

M-Link CSR (0040 - 005F)

M-Link CSR

0042 - FVME_REG_DEVICE_ID (D100)

0050 - FVME_REG_SERIAL_ID [63:0], 64 bit

0054 - FVME_REG_TEMPERATURE

0056 - FVME_REG_FW_VER

0057 - FVME_REG_FW_REV

Timers (0060 - 007F) (V2 only)

0060 - Timer frequency, Hz, 64-bit

0064 - XON time, 64-bit

0068 - XOFF time, 64-bit

Statistic Counters (0080 - 009F)

Statistic Counters: 32-bit, read only

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VME M-Link MLinkRegisters