= BPM4100 module registers =

Hardware: [[BPM4100]]

Registers are 16 bit width. 32-bit and 64-bit data is packed as following:
||Reg #||64-bit word||
||0x70||bits 15:0||
||0x71||bits 31:16||
||0x72||bits 47:32||
||0x73||bits 63:48||

== Register I/O ==

||0x40 - 0x5F||[[MlinkCsr|M-Link CSR]]||
||0x60 - 0xFF||BPM registers||

Reg 0x40, Control, R/W
 . bit 0-11 unused
 . bit 12 - disable 0xFEFE address decode '''new'''
 . bit 13 - toggle 0 to 1 causes thermometer reset and ID reread
 . bit 14 - trigger mastering enable(sending through diffpairs) 
 . bit 15 - run enable

Reg 0x42, Setup, RO
 . bit 15-8 - [[DeviceId|device id]] (0xB7)
 . bit 7-0 = reserved (0)

Reg 0x50, 64-bit Board Serial Number (DS18B20), RO

Reg 0x54, current temperature, RO

Reg 0x55, reserved, RO

Reg 0x56, 16-bit, firmware version number, RO

Reg 0x57, 16-bit, firmware revision number, RO

Reg 0x58 ... 5D, Link statistics, RO
 . 0x58 - link error 1 (T)
 . 0x59 - link error 2 (R)
 . 0x5A - link error 3 (O)
 . 0x5B - CRC error 1 (T)
 . 0x5C - CRC error 2 (R)
 . 0x5D - CRC error 3 (O)

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Reg 0x60 - Run status , RO
 . bit 0(lsb) - SPILL wait state
 . bit 1 - SPILL state
 . bit 2 - RAM Full
 . bit 3 - timeout SPILL end
 . bit 4-15 - unused

Reg 0x61 - Link status, RO
 . bit 0 - no_clock (R)
 . bit 1 - disconnected (R)
 . bit 2 - *LCF timeout (R)
 . bit 3 - *remote error (R)
 . bit 4 - reserved
 . bit 5 - no_clock (T)
 . bit 6 - disconnected (T)
 . bit 7 - *LCF timeout (T)
 . bit 8 - *remote error (T)
 . bit 9 - reserved
 . bit 10 - no_clock (O)
 . bit 11 - disconnected (O)
 . bit 12 - *LCF timeout (O)
 . bit 13 - *remote error (O)
 . bit 14 - reserved
 . bit 15 - reserved

Reg 0x62 - 32bit SPILL wait register, 20ns step, R/W

Reg 0x64 - 32bit SPILL length register, 20ns step, R/W

Reg 0x66 - 32bit Sample count*2 register, R/W

Reg 0x68 - Trig counter register (run enable bit clears counter), RO

Reg 0x6A - Enable mask for Table-based trigger registers(0x80..0x9F regs), R/W

Reg 0x6C - 32bit Timer trigger period register, 20ns step, R/W

Reg 0x6E - SPTRCTRL, Spill and Trigger Control register, R/W
 . bit 0 - Timer Trig enable
 . bit 1 - Table Trig enable
 . bit 2 - EXT Trig enable
 . bit 3 - NCU by B0 enable
 . bit 4 - NCU by Ext enable
 . bits 15:5 - unused

Reg 0x6F - TESTREG 
 . bit 0 - test ncu
 . bit 1 - test trig 
 . bit 2 - test trig counter enable (see also regs 0x6C, 0x6E)
 . bit 3 - enable 12.5 MHz on NIM1 and 6.25 MHz on NIM2 outputs 
 . bit 4-12 unused
 . bit 13 - reset timer trigger counter after spill_wait
 . bit 14 - select table triggers: 0 - BField, 1 - Timer (20 ns step)
 . bit 15 - enable counter instead of real adc data


Reg 0x70 - 64bit NCU TIME_STAMP register, 10ns step, RO

Reg 0x74 - 64bit END_RUN TIME_STAMP register, 10ns step, RO

Reg 0x78 - 64bit current TIME_STAMP register, 10ns step, RO

Reg 0x7C - 32bit current BField, RO

Reg 0x80 ... 0x9F - 16 x 32-bit Table Triggers registers, R/W

--(Reg 0x100 ..0x10F - 16 x 16-bit registers: statistics, clear by NCU, RO (TODO))--

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[[CategoryBpm4100|BPM4100]] [[CategoryMlinkRegisters|MLinkRegisters]]